Defect Detection and Defect-Tolerant Design of a Multi-port SRAM
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-7245-6_39
Reference14 articles.
1. Wang DP, Lin HJ, Hwang W (2013) A two-write and two-read multi-port SRAM with shared write bit-line scheme and selective read path for low power operation. J Low Power Electron 9(1):9–22
2. Ashok A, Ravi V (2017) ASIC design of MIPS based RISC processor for high performance. In: 2017 International conference on Nextgen electronic technologies: silicon to software (ICNETS2). IEEE, pp 263–269
3. Bhagyalakshmi V, Teja MR, Mohan CM (2014) Design and VLSI simulation of SRAM memory cells for multi-ported SRAM’s. Int J Res Electron Commun Technol
4. Liu L, Nagaraj P, Upadhyaya S, Sridhar R (2008) Defect analysis and defect tolerant design of multi-port srams. J Electron Test 24(1–3):165–179
5. Yang J, Wang B, Ivanov A (2004) Open defects detection within 6T SRAM cells using a no write recovery test mode. In 17th international conference on VLSI design. Proceedings. IEEE, pp 493–498
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