Investigation of Device and Circuit-Level Performances of Dielectric Engineered Dopingless SOI Schottky Barrier MOSFET
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-4495-8_4
Reference25 articles.
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2. J.M. Larson, J.P. Snyder, Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans. Electron Devices 53(5), 1048–1058 (2006)
3. S. Kale, P.N. Kondekar, Design and investigation of dielectric engineered dopant segregated Schottky barrier MOSFET with NiSi source/drain. IEEE Trans. Electron Devices 64(11), 4400–4407 (2017)
4. S. Kale, P.N. Kondekar, Impact of underlap channel and body thickness on the performance of DG-MOSFET with Si3N4 spacer. in IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 1–2 (2014)
5. H.C. Lin, M.F. Wang, C.Y. Lu, T.Y. Huang, Ambipolar Schottky barrier silicon-on-insulator metal–oxide–semiconductor transistors. Solid-State Electron. 47(2), 247–251 (2003)
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