Timed verification of the generic architecture of a memory circuit using parametric timed automata-Reference-Cited by-同舟云学术

Timed verification of the generic architecture of a memory circuit using parametric timed automata

Published:2008-11-05 Issue:1 Volume:34 Page:59-81
ISSN:0925-9856
Container-title:Formal Methods in System Design
language:en
Short-container-title:Form Methods Syst Des

Author:

Chevallier Remy,Encrenaz-Tiphene Emmanuelle,Fribourg Laurent,Xu Weiwen

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/s10703-008-0061-x.pdf

Reference18 articles.

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3. Alur R, Dill DL (1994) A theory of timed automata. Theor Comput Sci 126:183–235

4. Baclet M, Chevallier R (2005) Timed verification of the SPSMALL memory. In: 1th international conference memory technology and development, Giens, France, pp 1–2

5. Bozga M, Jianmin H, Maler O, Yovine S (2002) Verification of asynchronous circuits using timed automata. In: TPTS’02, ENTCS. vol 65

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