β-bit serial/parallel multipliers-Reference-Cited by-同舟云学术

β-bit serial/parallel multipliers

Published:1991-05 Issue:4 Volume:2 Page:219-233
ISSN:0922-5773
Container-title:Journal of VLSI signal processing systems for signal, image and video technology
language:en
Short-container-title:J VLSI Sign Process Syst Sign Image Video Technol

Author:

North Richard C.,Ku Walter H.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Information Systems,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/BF00925467.pdf

Reference31 articles.

1. R.W. Linderman, P.M. Chau, K.H. Ku and P.P. Reusens, “CUSP: A 2μm CMOS Digital Signal Processor,”IEEE Trans. on Solid State Circuits, vol. SC-20, no. 3, 1985, pp. 761–769.

2. K.C. Chew, P.M. Chau, W.H. Ku, “A Bit-Serial Floating-Point Complex Multiplier-Accumulator for Fault Tolerant Digital Signal Processing Arrays,”Inter. Conf. on Acoustics, Speech and Signal Processing (ICASSP), 1987, pp. 483–486.

3. P.B. Denyer and D. Renshaw,VLSI Signal Processing: A Bit-Serial Approach, Reading, MA: Addison-Wesley, 1985.

4. S.G. Smith and P.B. Denyer,Serial-Data Computation, Boston: Kluwer Academic, 1988.

5. N.R. Powell, J.M. Irwin, “A MOS Monolithic Chip for High Speed Flexible FFT Microprocessors,”IEEE Inter. Solid-State Circuits Conf. (ISSCC), 1975, pp. 18–19.

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