Author:
Cho Youngchul,Zergainoh Nacer-Eddine,Yoo Sungjoo,Jerraya Ahmed Amine,Choi Kiyoung
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Software
Reference29 articles.
1. Baghdadi A, Zergainoh N-E, Cesário W, Jerraya A (2002) Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems. IEEE Trans Softw Eng 28(9):822–831
2. Cesário W, Baghdadi A, Gauthier L, Lyonnard D, Nicolescu G, Paviot Y, Yoo S, Jerraya A, Diaz-Nava M (2002) Component-based design approach for multicore SoCs. Proc Des Autom Conf, pp 789–794
3. Chen Y-Y, Hsu Y-C, Kin C-T (1994) MULTIPAR: Behavioral partition for synthesizing multiprocessor architectures. IEEE Trans Very Large Scale Integration (VLSI) Syst 2(1):21–32
4. Cho Y, Lee G, Yoo S, Choi K, Zergainoh N-E (2003) Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design. In: Proceedings of design automation and test in Europe conference, pp 132–137, supplement
5. Cho Y, Zergainoh N-E, Yoo S, Choi K, Jerraya A (2005) Scheduler implementation in MP SoC design. In: Proceedings of Asia and South Pacific design automation conference, pp 151–156
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献