Reducing the complexity of instruction-level power models for VLIW processors
Author:
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Software
Link
http://link.springer.com/content/pdf/10.1007/s10617-006-9045-5.pdf
Reference30 articles.
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2. Lee, T., V. Tiwari, and S. Malik. Power Analysis and Minimization Techniques for Embedded DSP Software. In IEEE Transactions on VLSI Systems, vol. 5, no. 1, pp. 123–135, 1997.
3. Sami, M., D. Sciuto, C. Silvano, and V. Zaccaria. An Instruction-Level Energy Model for Embedded VLIW Architectures. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. r92, September 2002, pp. 998–1010.
4. Bona, A., M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon. Energy Estimation and Optimization of Embedded VLIW Processors Based on Instruction Clustering. In Proceedings of the 39th Design Automation Conference DAC’02, June 2002, pp. 886–891.
5. Tiwari, V., S. Malik, A. Wolfe, and M. Lee. Instruction Level Power Analysis and Optimization of Software. In J. VLSI Signal Processing, pp. 1–18, 1996.
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