Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter-Reference-Cited by-同舟云学术

Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

Published:2020-05-14 Issue:5 Volume:12 Page:5513-5524
ISSN:1868-5137
Container-title:Journal of Ambient Intelligence and Humanized Computing
language:en
Short-container-title:J Ambient Intell Human Comput

Author:

Sakthivel R.,Ragunath G.

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Link

https://link.springer.com/content/pdf/10.1007/s12652-020-02062-3.pdf

Reference21 articles.

1. Akbari O, Kamal M, Afzali-Kusha A, Pedram M (2016) RAP-CLA: a reconfigurable approximate carry look-ahead adder. IEEE Trans Circ Syst II Express Briefs 65(8):1089–1093

2. Balasubramanian P, Maskell D, Mastorakis N (2018) Low power robust early output asynchronous block carry lookahead adder with redundant carry logic. Electronics 7(10):243

3. Bedrij OJ (1962) Carry-select adder. IRE Trans Electronic Comput 3:340–346

4. Chang TY, Hsiao MJ (1998) Carry-select adder using single ripple-carry adder. Electron Lett 34(22):2101–2103

5. De D, Das JC (2017) Design of novel carry save adder using quantum dot-cellular automata. J Comput Sci 22:54–68

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