Comparison and extension of high performance adders for hybrid and error tolerant applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
General Computer Science
Link
https://link.springer.com/content/pdf/10.1007/s12652-021-03574-2.pdf
Reference25 articles.
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2. Garg B, Dutt S, Sharma GK (2016) Bit-width-aware constant-delay run-time accuracy programmable adder for error-resilient applications. Microelectron J 50:1–7. https://doi.org/10.1016/j.mejo.2016.01.002
3. Geetha S, Amritvalli P (2017) High speed error tolerant adder for multimedia applications. J Electron Test 33(5):675–688. https://doi.org/10.1007/s10836-017-5680-y
4. Gupta V, Mohapatra D, Raghunathan A, Roy K (2012) Low-power digital signal processing using approximate adders. IEEE Trans Comput Aided Des Integr Circuits Syst 32(1):124–137. https://doi.org/10.1109/TCAD.2012.2217962
5. Hu J, Li Z, Yang M, Huang Z, Qian W (2019) A high-accuracy approximate adder with correct sign calculation. Integration 65:370–388. https://doi.org/10.1016/j.vlsi.2017.09.003
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