On reconfgurable co-processing units

Author:

Hartenstein Reiner W.,Herz Michael,Hoffmann Thomas,Nageldinger Ulrich

Publisher

Springer Berlin Heidelberg

Reference6 articles.

1. R. Hartenstein, et al.: An Embedded Accelerator for Real World Computing; VLSI'97, Gramado, Brazil, August 26-29, 1997.

2. R. Hartenstein, et al.: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. IEEE Int'l Conf. on Innovative Systems in Silicon; Austin, Oct. 96.

3. Andre DeHon: Reconfigurable Architectures for General-Purpose Computing; Technical Report 1586, MIT Artificial Intelligence Laboratory, September, 1996.

4. R. W Hartenstein, et al.: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; ASP-DAC'95, Chiba, Japan, Aug. 29–Sept. l, 1995.

5. A. Yeung, J. Rabaey: A Reconfigurable Data-Driven Multiprocessor Architecture for Rapid Prototyping of High Throughput DSP Algorithms; HICSS-26, Vol. 1, IEEE Computer Society Press, 1993.

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1. Coarse-Grained Reconfigurable Array: Architecture and Application Mapping;IPSJ Transactions on System LSI Design Methodology;2011

2. Computing Platforms;Embedded Systems Design;2005

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