1. R. Lyons, “A bit-serial VLSI architectural methodology for signal processing,”VLSI'81, Ed. J.P. Gray. New York: Academic Press, 1981, pp. 131–140.
2. P. Denyer and D. Renshaw,VLSI Signal Processing: A Bit-Serial Approach, Reading, MA: Addison-Wesley, 1985.
3. M.J. Irwin and R.M. Owens, “Digit pipelined arithmetic: A tutorial,”IEEE Computer Magazine, April 1987, pp. 61–73.
4. S.G. Smith and P.B. Denyer,Serial-Data Computation, Kluwer Academic Publishers, 1988.
5. S. Knowleset al., “Bit-level systolic arrays for IIR filtering,”Proc. of the Intl. Conf. on Systolic Arrays, San Diego, CA, May 1988, pp. 653–663.