The Optimum Network on Chip Architectures for Video Object Plane Decoder Design-Reference-Cited by-同舟云学术

The Optimum Network on Chip Architectures for Video Object Plane Decoder Design

Published:2006 Issue: Volume: Page:75-85
ISSN:0302-9743
Container-title:Parallel and Distributed Processing and Applications
language:
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Author:

Ngo Vu-Duc,Nguyen Huy-Nam,Choi Hae-Wook

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/11946441_12

Reference17 articles.

1. ITRS. International technology roadmap for semiconductors, edition (2005), http://public.itrs.net/

2. Benini, L., et al.: Networks On Chips: A new SoC paradigm. IEEE computer (January 2002)

3. Bertozzi, D., et al.: Network on Chip Design for Gigascale Systems on Chips. In: Zurawski, R. (ed.) Industrial Technology Handbook, pp. 49–80. CRC Press, Boca Raton (2004)

4. Guerrier, P., et al.: A generic architecture for on-chip packet-switched interconnectio. In: Proc. of Design Automation and Test in Europe Conf., pp. 250–256 (August 2000)

5. Kumar, S., et al.: A Network on Chip Architecture and Design Methodology. In: Proc of. Int’l Symp. VLSI, pp. 117–124 (2002)

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