Author:
Thibeault Claude,Savaria Yvon,Houle Jean -Louis
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference18 articles.
1. W.R. Moore, ?A review of fault-tolerant techniques for the enhancement of integrated circuit yield,?Proc. IEEE, vol. 74, pp. 684?698, May 1986.
2. G. Saucier, J.-L. Patry, E.-F. Kouka, T. Midwinter, P. Ivey, M. Huch, and M. Glesner, ?Defect tolerance in a wafer scale array for image processing,?Defect and Fault-Tolerance in VLSI Systems, New York: Plenum Press, pp. 327?338, 1989.
3. R.M. Lea, ?A WSI image processor,?Wafer Scale Integration, Boston: Kluwer Academic, pp. 193?252, 1989.
4. R.L. Wadsack, ?VLSI: How much fault coverage is enough?,?Digest of Papers, 1981 Intern. Test Conf., pp. 547?554, October 1981.
5. I. Koren and D. Pradhan, ?Modeling the effect of redundancy on yield and performance of VLSI systems,?IEEE Trans. on Computers, vol. C-37, pp. 344?355, March 1987.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems;2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems;2010-10