1. Lackey, D.E., Zuchowski, P.S., Bednar, T.R., Stout, D.W., Gould, S.W., Cohn, J.M.: Managing power and performance for system-on-chip designs using voltage islands. In: Proc. ICCAD 2002, pp. 195–202 (2002)
2. Huang, W., Stan, M.R., Skadron, K., Sankaranarayanan, K., Ghosh, S., Velusamy, S.: Compact thermal modeling for temperature-aware design. In: Proc. DAC 2004, pp. 878–883 (2004)
3. Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T., Irwin, M.J.: Thermal-aware floorplanning using genetic algorithms. In: Proc. ISQED 2005, pp. 634–639 (2005)
4. Cong, J., Wei, J., Zhang, Y.: A thermal-driven floorplanning algorithm for 3D ICs. In: Proc. ICCAD 2004, pp. 306–313 (2004)
5. Ekpanyapong, M., Healy, M.B., Ballapuram, C.S., Lim, S.K., Lee, H.S.: Thermal-aware 3D microarchitectural floorplanning. CERCS Technical Reports, GIT-CERCS-04-37 (2004)