Power-Clock Gating in Adiabatic Logic Circuits-Reference-Cited by-同舟云学术

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Power-Clock Gating in Adiabatic Logic Circuits

Published:2005 Issue: Volume: Page:638-646
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
Short-container-title:

Author:

Teichmann Philip,Fischer Jürgen,Henzler Stephan,Amirante Ettore,Schmitt-Landsiedel Doris

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/11556930_65.pdf

Reference8 articles.

1. Chandrakasan, A.P., Brodersen, R.W.: Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE 83(4), 498–523 (1995)

2. Tschanz, J.W., Narendra, S.G., Ye, Y., Bloechel, B.A., Borkar, S., De, V.: Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microporcessors. IEEE Journal of Solid-State Circuits 38(11), 1838–1845 (2003)

3. Henzler, S., Nirschl, T., Skiathitis, S., Berthold, J., Fischer, J., Teichmann, P., Bauer, F., Georgakos, G., Schmitt-Landsiedel, D.: Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power- Down Times. In: IEEE International Solid-State Circuits Conference, p. 13 (2005)

4. Moon, Y., Jeong, D.: An Efficient Charge Recovery Logic Circuit. IEEE Journal of Solid-State Circuits 31(4), 514–522 (1996)

5. Vetuli, S., Di Pascoli, L.M.: Reyneri: Positive feedback in adiabatic logic. Electronics Letters 32(20), 1867–1869 (1996)

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Clock System Architecture for Digital Circuits;International Conference on Intelligent Computing and Smart Communication 2019;2019-12-20

2. Power-Clock Gating;Adiabatic Logic;2012

3. Low-Power Register File Based on Adiabatic Logic Circuits;Lecture Notes in Computer Science;2006

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