An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks
Author:
Funder
Kwangwoon University
Publisher
Springer Science and Business Media LLC
Subject
Artificial Intelligence
Link
http://link.springer.com/article/10.1007/s10489-018-1246-7/fulltext.html
Reference45 articles.
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3. Jantch A, Tenhunen H (2003) Networks on chip. Kluwer Academic Publishers, Norwell
4. Atienza D, Angiolini F, Murali S et al (2008) Network-on-chip design and synthesis outlook. VLSI J 41:340–359
5. Tsai WC, Lan YC, Hu YH, et al (2012) Networks on chips: structure and design methodologies. Hindawi J Electric Comput Eng, Article ID 509465, 15 pp
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