A deterministic digital calibration technique for pipelined ADCs using a non-nested algorithm-Reference-Cited by-同舟云学术

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A deterministic digital calibration technique for pipelined ADCs using a non-nested algorithm

Published:2022-01-08 Issue:3 Volume:110 Page:557-568
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Ramamurthy Chinmaye^ORCID,Padma Surya,Parikh Chetan,Sen Subhajit

Funder

ISRO University Research funding (RESPOND) program

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s10470-021-01961-5.pdf

Reference20 articles.

1. Karanicolas, A. N., Lee, H. S., & Bacrania, K. L. (1993). A 15-b 1-m sample/s digitally self-calibrated pipelined ADC. IEEE Journal of Solid -State Circuits, 28(12), 1207–1215.

2. Sahoo, B., & Razavi, B. (2011). A 10-bit 1-GHz 33-mW CMOS ADC. IEEE Journal of Solid-State Circuits, 48(6), 1442–1452.

3. Chuang, S. Y., & Sculley, T. L. (2002). A digitally self-calibrating 14-bit 10-MHz CMOS pipelined ADC. IEEE Journal of Solid-State Circuits, 37(6), 674–683.

4. Wang, X., Hurst, P. J., & Lewis, S. H. (2004). A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE Journal of Solid-State Circuits, 39(11), 1799–1808.

5. Erdogan, O. E., Hurst, P. J., & Lewis, S. H. (1999). A 12 b digital-background-calibrated algorithmic ADC with-90 dB THD. IEEE Journal of Solid-State Circuits, 34(12), 1812–1820.

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1. A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters;2022 Iranian International Conference on Microelectronics (IICM);2022-12-20

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