A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-023-02147-x.pdf
Reference42 articles.
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2. Prasad, G., & Anand, A. (2015). Statistical analysis of low-power SRAM cell structure. Analog Integrated Circuits and Signal Processing, 82, 349–358.
3. Mukherjee, R., Saha, P., Chakrabarti, I., Dutta, P. K., & Ray, A. K. (2018). Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos. Expert Systems with Applications, 101, 159–175.
4. Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories. Wireless Personal Communications, 108(4), 2311–2339.
5. Gavaskar, K., & Ragupathy, U. S. (2014). An efficient design and comparative analysis of low power memory cell structures. In 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) (pp. 1–5). IEEE.
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