All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-011-9654-1.pdf
Reference16 articles.
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2. Chung, C.-C., & Lee, C.-Y. (2003). An all-digital phase-locked loop for high-speed clock generation. IEEE Journal of Solid-State Circuits, 38(2), 347–351.
3. Olsson, T., & Nilsson, P. (2004). A digitally controlled PLL for SoC applications. IEEE Journal of Solid-State Circuits, 39(5), 751–760.
4. Tierno, J. A., Rylyakov, A. V., & Friedman, D. J. (2007). A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI. IEEE Journal of Solid-State Circuits, 43(1), 42–51.
5. Chen, P.-L., Chung, C.-C., Yang, J.-N., & Lee, C.-Y. (2006). A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE Journal of Solid-State Circuits, 41(6), 1275–1285.
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1. A wide supply voltage range and low-power all-digital clock generator;Analog Integrated Circuits and Signal Processing;2013-01-06
2. A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor;IEICE Electronics Express;2012
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