Optimizing performances of switched current memory cells through a heuristic-Reference-Cited by-同舟云学术

Optimizing performances of switched current memory cells through a heuristic

Published:2006-11-04 Issue:2 Volume:50 Page:115-126
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Fakhfakh Mourad,Loulou Mourad,Masmoudi Nouri

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-006-9009-5.pdf

Reference15 articles.

1. C. Toumazou, J.B. Huges, and N.C. Battersby, Switched Currents: an Analogue Technique for Digital Technology, Peter Pregnius, 1993.

2. J.B. Hughes, A. Worapishet, and C. Toumazou, ``Switched-capacitors versus switched-currents: A theoretical comparison.'' ISCAS 2000-IEEE Inter. Symp. on Circuits and Systems, May 28–31, 2000, Geneva, Switzerland, pp. II-409-12.

3. O. Oliaei and P. Loumeau, ``Current mode Class AB CMOS using floating voltage-source.'' Electronics Letters, Vol. 32, no. 17, pp. 1526–1527, 15 August 1996.

4. I. O'Connor and A. Kaiser, ``Automated synthesis of current-memory cells.'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, April 2000.

5. A.R. Con, P.K. Coulman, R.A. Haring, G.L. Morrill, and C. Visweswariah, ``Optimisation of custom MOS circuits by transistor sizing.'' ICCAD'96, November 10–14, 1996, San-Jose, CA, 174.

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