MOS Amplifier Design Methodology for Optimum Performance-Reference-Cited by-同舟云学术

MOS Amplifier Design Methodology for Optimum Performance

Published:2018-08-22 Issue:4 Volume:66 Page:478-490
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Mondal Abir J.¹,Bhattacharjee Paromita¹²,Chakraborty Pinaki³,Bhattacharyya Bidyut K.⁴

Affiliation:

1. Department of Electronics and Communication Engineering, National Institute of Technology, Arunachal Pradesh, 791 112, India

2. Indian Institute of Technology Guwahati, Assam, 781 039, India

3. Department of Basic and Applied Science, National Institute of Technology, Arunachal Pradesh, 791 112, India

4. Department of Electronics and Communication Engineering, National Institute of Technology, Agartala, 799 046, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2018.1506267

Reference16 articles.

1. A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

2. A. I. A. Cunha, O. C. Gouveia-Filho, M. C. Schneider, and C. Galup-Montoro, “A current-based model for the MOS transistor,” in Proceedings of 1997 IEEE International Symposium on Circuits and Systems, 1997. ISCAS’97, Vol. 3, Jun. 1997, pp. 1608–11.

3. An MOS transistor model for analog circuit design

4. R. Oliveira Pinto, A. Cunha, M. Schneider, and C. Galup-Montoro, “An amplifier design methodology derived from a MOSFET current-based model,” in Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998. ISCAS ‘98, Vol. 1, May 1998, pp. 301–4.

5. F. A. Farag, “CMOS amplifier design methodology for optimum slew rate,” in 11th Mediterranean Electrotechnical Conference, 2002. MELECON 2002, pp. 532–6.