Author:
Jalalifar Majid,Byun Gyung-Su
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference48 articles.
1. Lee, K., Lee, S., & Yoo, H. (2006). Low-power network-on-chip for high performance SoC design. IEEE Transactions on VLSI Systems,14(2), 148–160.
2. Truong, D. N., Cheng, W. H., Mohsenin, T., Yu, Z., Jacobson, A. T., et al. (2009). A 167-processor computational platform in 65 nm CMOS. IEEE Journal of Solid-State Circuits,44(4), 1130–1144.
3. Lee, S. -K., Lee, S. -H., Sylvester, D., Blaauw, D. & Sim, J. -Y. (2013). A 95fJ/b current-mode transceiver for 10 mm on-chip interconnect. In Proceedings of IEEE ISSCC Digest of Technical Papers (pp. 262–263).
4. Höppner, S., Walter, D., Hocker, T., Henker, S., Hänzsche, S., et al. (2015). An energy efficient multi-Gbit/s NoC transceiver architecture with combined AC/DC drivers and stoppable clocking in 65 nm and 28 nm CMOS. IEEE Journal of Solid-State Circuits,50(3), 749–762.
5. Chen, M. -S., Chang, M. -C. F., & Yang, C. -K. K. (2015). A low-PDP and low-area repeater using passive CTLE for on-chip interconnects. In Symposium on VLSI Circuits (pp. C244–C245).
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