Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process-Reference-Cited by-同舟云学术

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

Published:2009-10-23 Issue:1 Volume:65 Page:61-66
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Oliveira Vlademir J. S.,Oki Nobuo

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-009-9412-9.pdf

Reference9 articles.

1. Tanno, K., Ishizuka, O., & Tang, Z. (2000). Four-quadrant CMOS current-mode multiplier independent of device parameters. IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, 47(5), 473–477.

2. Oliaei, O., & Loumeau, P. (1996). Four-quadrant class AB CMOS current multiplier. Electronics Letters, 32(25), 2327–2329.

3. Ravindran, A., Ramarao, K., Vidal, E., & Ismail, M. (2001). Compact low voltage four quadrant CMOS current multiplier. Electronics Letters, 37(24), 1428–1429.

4. Arthansiri, T., Kasemsuwan, V., & Ahn, H. K. (2005) A ±1.5 V high frequency four quadrant current multiplier. In IEEE international symposium on circuits and systems, ISCAS 2005, Kobe, Japan (Vol. 2, pp. 1016–1019) 23–26 May, 2005.

5. Han, G., & Sánchez-Sinencio, E. (1998). CMOS transconductance multipliers: A tutorial. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 45(12), 1550–1562.

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