A 1 mW power-efficient high frequency CML 2:1 divider-Reference-Cited by-同舟云学术

A 1 mW power-efficient high frequency CML 2:1 divider

Published:2011-08-12 Issue:3 Volume:71 Page:515-523
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Zhou Chunyuan,Zhang Lei,Wang Hongrui,Zhang Li,Wang Yan,Yu Zhiping,Qian He

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-011-9673-y.pdf

Reference18 articles.

1. Tiebout, M. (2004). A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider. IEEE Journal of Solid-State Circuits, 39(7), 1170–1174.

2. Yamamoto, K., & Fujishima, M. (2004). 55 GHz CMOS frequency divider with 3.2 GHz locking range. Proceeding of the 30th European Solid-State Circuits Conference (ESSCIRC), 2004, (pp. 135–138).

3. Yuan, M., Skafidas, E., Evans, R., & Mareels, I. (2008). Analysis and design of a 50-GHz 2:1 CMOS CML static frequency divider based on LC-tank. European Microwave Integrated Circuit Conference(EuMIC), 2008, (pp. 64–67).

4. Kim, D. D., Jonghae, K., & Choongyeun, C. (2008). A 94 GHz locking hysteresis-assisted and tunable CML static divider in 65 nm SOI CMOS. IEEE International Solid-State Circuits Conference(ISSCC), 2008, (pp. 460–628).

5. Tai-Cheng, L., Hua-Chin, L., Keng-Jan, H., Yen-Chun, H., & Guan-Jun, C. (2005). A 40-GHz distributed-load static frequency divider. Asian Solid-State Circuits Conference, 2005, (pp. 205–208).

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