A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT- $$\Updelta\Upsigma$$ Δ Σ ADC with 1.5 cycle quantizer delay and improved STF-Reference-Cited by-同舟云学术

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT- $$\Updelta\Upsigma$$ Δ Σ ADC with 1.5 cycle quantizer delay and improved STF

Published:2013-04-25 Issue:2 Volume:78 Page:275-286
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Balagopal Sakkarapani,Zhu Kehan,Saxena Vishal

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-013-0066-2.pdf

Reference22 articles.

1. Ortmanns, M. & Gerfers, F. (2006). Continuous-time sigma-delta A/D conversion: Fundamentals, performance limits and robust implementations, vol. 21. Berlin: Springer.

2. Schreier, R., & Temes, G. C. (2005). Understanding delta-sigma data converters. Piscataway: IEEE press.

3. Bolatkale, M. et al. (2011). A 4 GHz CT $$\Updelta\Upsigma$$ Δ Σ ADC with 70 dB DR and −74 dBFS THD in 125MHz BW. In ISSCC digest of technical papers, pp. 470–471.

4. Ke, Y., Craninkx, J., & Gielen, G. (2009). Multi-standard continuous-time sigma–delta converters for 4G radios. In Circuits and systems for future generations of wireless communications (pp. 203–221). Springer.

5. Kauffman, J. G., Witte, P., Becker, J., & Ortmanns, M. (2011). An 8 mw 50 ms/s ct δσ modulator with 81 db sfdr and digital background dac linearization. In Solid-state circuits conference digest of technical papers (ISSCC), 2011 IEEE International, pp. 472–474. San Francisco: IEEE.

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