An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization-Reference-Cited by-同舟云学术

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An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization

Published:2011-02 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE International Solid-State Circuits Conference
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Author:

Kauffman John G.,Witte Pascal,Becker Joachim,Ortmanns Maurits

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5740653/5746170/05746402.pdf?arnumber=5746402

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 13-Level SC DAC Achieving High Linearity With a Simple DEM for Wideband CT DSMs;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08

2. On the Intrinsic Linearity Limitations of Single-Bit Delta Sigma Modulators;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper;2021 18th International SoC Design Conference (ISOCC);2021-10-06

4. Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples;ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC);2021-09-13

5. Multi-bit Sigma-Delta TDC Architecture with Improved Linearity;Journal of Electronic Testing;2013-10-04

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