Spurs in subsampling fractional PLLs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-019-01489-9.pdf
Reference9 articles.
1. Gupta, M., & Song, B.-S. (2006). A 1.8-GHz spur-cancelled fractional-n frequency synthesizer with LMS-based DAC gain calibration. IEEE Journal of Solid State Circuits, 41, 2842–2851.
2. Hsu, C.-W., Tripurari, K., Yu, S.-A., & Kinget, P. R. (2015). A sub-sampling-assisted phase-frequency detector for low-noise PLLs with robust operation under supply interference. IEEE Transactions on Circuits and Systems. I Regular Pappers, 62, 90–99.
3. Gao, X., Klumperink, E. A. M., Bohsali, M., & Nauta, B. (2009). A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by $$N^{2}$$. IEEE Journal of Solid State Circuits, 44, 3253–3263.
4. Liao, D., Dai, F. F., Nauta, B., & Klumperink, E. A. M. (2018). A 2.4-GHz 16-phase sub-sampling fractional-N PLL with robust soft loop switching. IEEE Journal of Solid State Circuits, 53, 715–727.
5. Liao, D., Dai, F. F., Nauta, B., & Klumperink, E. (2017). Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking. In: 2017 IEEE custom integrated circuits conference (CICC). IEEE, pp. 1–4
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1. Moving average filter for spur reduction in subsampling fractional PLLs;Analog Integrated Circuits and Signal Processing;2021-10-04
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