Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-011-9621-x.pdf
Reference21 articles.
1. Sinsky, J. H., Duelk, M., & Adamiecki, A. (2005). High-speed electrical backplane transmission using duobinary signaling. IEEE Transactions on Microwave Theory and Techniques, 53(1), 152–160.
2. Lee, J., Chen, M.-S, & Wang, H.-D. (2008). A 20-Gb/s duobinary transceiver in 90-nm CMOS. In IEEE international solid-state circuits conference. Digest of technical papers, 3–7 Feb 2008, pp. 102–103.
3. Farjad-Rad R., Yang C.K., Horowitz M., & Lee T. (2000). A 0.3 μm CMOS—Gb/s 4-PAM serial link transceiver. IEEE Journal on Solid-State Circuits, 35, 757–764.
4. Foley, D. J., & Flynn, M. P. (2002). A low power 8-PAM serial transceiver in 0.5/μm digital CMOS. IEEE Journal of Solid State Circuits, 37(3), 310–316.
5. Savoj, J., & Razavi, B. (2001). Design of half-rate clock and data recovery circuits for optical communication systems. In 38th annual design automation conference, Las Vegas, NV, pp. 121–126.
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