An I/Q channel 12-bit 120 MS/s CMOS DAC with deglitch circuits

Author:

Seon Jong-Kug,Ha Seong-Min,Yoon Kwang Sub

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Improved performance 6-bit 3.5 GS/s unary CS-DAC using glitch reduction;International Journal of Electronics Letters;2019-06-10

2. Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015

3. A low-glitch binary-weighted DAC with delay compensation scheme;Analog Integrated Circuits and Signal Processing;2014-02-05

4. An I/Q DAC with gain matching circuit for a wireless transmitter;Journal of Semiconductors;2013-06

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