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Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC

  • Published:2015 Issue: Volume: Page:1-5
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chou Fang-Ting,Hung Chung-Chih

Funder

Ministry of Science and Technology.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 29 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low Power Current Steering DAC Using 45nm CMOS Technology;2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2024-04-26

2. Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique;International Journal of Circuit Theory and Applications;2023-11-30

3. A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation;AEU - International Journal of Electronics and Communications;2023-03

4. CNTFET based 4-bit thermometer current steering digital to analog converter: design and analysis;Analog Integrated Circuits and Signal Processing;2023-01-12

5. Dynamic Switching Compensation Technique Mitigating Code-Dependent Switching Distortion in CS-DACs;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24
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