A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS-Reference-Cited by-同舟云学术

A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS

Published:2008-03-07 Issue:1-2 Volume:56 Page:43-51
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Heedley Perry L.,Dyer Kenneth C.,Matthews Thomas W.,Isakanian Patrick,Thanh Chuc

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-007-9081-5.pdf

Reference14 articles.

1. Abo, A., & Gray, P. R. (1998). A 1.5V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter. In VLSI 1998 (pp. 166–169). Honolulu, Hawaii: IEEE Symposium on VLSI Circuits.

2. Lewis, S. H., Fetterman, H. S., Gross, G. F. Jr., Ramachandran, R., & Viswanathan, T. R. (1992). A 10-b 20-Msample/s analog-to-digital converter. IEEE Journal of Solid-State Circuits, 27(3), 351–358.

3. Samavati, H., Hajimiri, A., Shahani, A., Nasserbakht, G., & Lee, T. (1998). Fractal capacitors. In ISSCC 1998 (pp. 256–257). San Francisco, CA: IEEE Soild-State Circuits Conference.

4. Heedley, P. L., & Dyer, K. C. (2005). Biasing technique using thin and thick oxide transistors. U.S. Patent 6,977,543, Dec. 20, 2005.

5. Park, Y. -I., Karthikeyan, S., Tsay, F., & Bartolome, E. (2001). A 10b 100MSample/s CMOS Pipelined ADC with 1.8V Power Supply. In ISSCC 2001 (pp. 130–131, 439). San Francisco, CA: IEEE Soild-State Circuits Conference.

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