An ultra low die area 8-b ADC and its generic calibration logic-Reference-Cited by-同舟云学术

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An ultra low die area 8-b ADC and its generic calibration logic

Published:2011-07-14 Issue:3 Volume:70 Page:323-335
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Petrellis Nikos,Birbas Michael

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-011-9686-6.pdf

Reference20 articles.

1. Chan, B., Oyama, B., Monier, C. & Guiterrez, A. (2007). An ultra-wideband 7-Bit 5 Gsps ADC implemented in submicron InP HBT technology. In Proceedings of the IEEE int. conf. on compound semiconductor integrated circuit symposium 2007, 14–17, pp 1-3.

2. Gethmiri, S., & Salama, T. (2010). An 8-bit 12.5-G sample/s SiGe ADC. Analog Integrated Circuits and Signal Processing, 63, 381–395.

3. Saponara, S. (2011). Configurable array of low-complex SAR ADCs. To be published at Analog Integrated Circuits and Signal Processing, received Feb 2011.

4. Ay, S. (2011). A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS. Analog Integrated Circuits and Signal Processing, 66, 213–221.

5. Agnes, A., Bonnizoni, E., Malcovati, P., & Maloberti, F. (2010). An ultra-low power successive approximation A/D converter with time–domain comparator. Analog Integrated Circuits and Signal Processing, 64, 183–190.

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