A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock-Reference-Cited by-同舟云学术

A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

Published:2012-10-18 Issue:2 Volume:74 Page:355-364
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Park Hyung-Gu,Kim SoYoung,Lee Kang-Yoon

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-012-9976-7.pdf

Reference20 articles.

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2. Yamguchi, K., Hori, Y., Nakajima, K., Suzuki, K., Mizuno, M., Hayama, H. (2009). A 2.0 Gb/s clock-embedded interface for full-HD 10b 120 Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. IEEE ISSCC Digest of Technical Papers, pp. 192–193.

3. Lee, T. H., Donnelly, K. S., Ho, J. T. C., Zerbe, J., Johnson, M. G., & Ishikawa, T. (1994). A 2.5 V CMOS delay-locked loop for an 18 Mbit, 500 MB/s DRAM. IEEE Journal of Solid-State Circuits, 29, 1491–1496.

4. Sidiropoulos, S., & Horowiz, M. A. (1997). A semi-digital dual delay-locked loop. IEEE Journal of Solid-State Circuits, 32, 1683–1692.

5. Coban, A. L., Koroglu, M. H., & Ahmed, K. A. (2005). A 2.5–3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs. IEEE Journal of Solid-State Circuits, 40(9), 1940–1947.

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