A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOS-Reference-Cited by-同舟云学术

A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOS

Published:2013-04-27 Issue:1 Volume:76 Page:91-102
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Bui Long Thanh,Chau Tran-Thuyen,Lee Jong-Wook

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-013-0075-1.pdf

Reference22 articles.

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2. Lee, J., Mingchung, L., & Huaide, W. (2008). A 75-GHz phase-locked loop in 90-nm CMOS technology. IEEE Journal of Solid-State Circuits, 43(6), 1414–1426.

3. Cao, C., Ding, Y., & O, K. K. (2007). A 50-GHz phase-locked loop in 0.13 μm CMOS. IEEE Journal of Solid-State Circuits, 42, 1649–1656.

4. Voinigescu, S. P., Aroca, R., Dickson, T. O., Nicolson, S. T., Chalvatzis, T., Chevalier, P., Garcia, P., Garnier, C. & Sautreuil, B. (2007). Towards a sub-2.5 V, 100-Gb/s serial transceiver. In: IEEE Custom Integrated Circuits Conference (pp 471–478).

5. Plouchart, J. O., Kim, J., Recoules, H., Zamdmer, N., Yue Tan, Sherony, M., Ray, A., & Wagner L. (2003, June). A power-efficient 33 GHz 2:1 static frequency divider in 0.12-μm SOI CMOS. In: Proc. IEEE Radio Frequency Integrated Circuits Symposium, (pp. 329–332).

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