On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs-Reference-Cited by-同舟云学术

On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs

Published:2010-06-23 Issue:1 Volume:67 Page:21-29
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Korhonen Esa,Kostamovaara Juha

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-010-9496-2.pdf

Reference18 articles.

1. Bernard, S., Azais, F., Bertrand, Y., & Renovell, M. (2003). On-chip generation of ramp and triangle-wave stimuli for ADC BIST. Journal of Electronic Testing, 19(4), 469–479.

2. Chuang, H. M., Thei, K. B., Tsai, S. F., Lu, C. T., Liao, X. D., Lee, K. M., Chen, H. R., & Liu, W. C. (2003). A comprehensive study of polysilicon resistors for CMOS ULSI applications. Superlattices and Microstructures, 33(4), 193–208.

3. Dallet, D., & Machado da Silva, J. (eds) (2005). Dynamic characterisation of analogue-to-digital converters. The springer international series in engineering and computer science (Vol. 860). US: Springer.

4. IEEE. (2001). IEEE standard for terminology and test methods for analog-to-digital converters. IEEE Std 1241-2000.

5. Jin, L., Chen, D., & Geiger, R. L. (2007). SEIR linearity testing of precision A/D converters in nonstationary environments with center-symmetric interleaving. IEEE Transactions on Instrumentation and Measurement, 51(1), 138–143.

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