A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme-Reference-Cited by-同舟云学术

A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme

Published:2022-05-10 Issue:1 Volume:112 Page:185-196
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Jung Inho,Bae Sunghyun,Lee Sinho,Lee Minjae^ORCID

Funder

National Research Foundation of Korea

Samsung Electronics

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s10470-022-02016-z.pdf

Reference11 articles.

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2. Gao, X., Burg, O., Wang, H., Wu, W., Tu, C.-T., Manetakis, K., et al. (2016). A 2.7-to-4.3 GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. In IEEE international solid-state circuits conference digest of technical papers (pp. 174–175).

3. Chen, P., Huang, X., Liu, Y.-H., Ding, M., Zhou, C., Ba, A., et al. (2015). Design and built- in characterization of digital-to-time converters for ultra-low-power ADPLLs. In IEEE 41st European solid-state circuits conference (pp. 283–286).

4. Markulic, N., Raczkowski, K., Wambacq, P., & Craninckx, J. (2014). A 10-bit, 550-fs step digital-to-time converter in 28 nm CMOS. In 40th European solid-state circuits conference (pp. 79–82).

5. He, Y., Liu, Y.-H., Kuramochi, T., Heuvel, J., Busze, B., Markulic, N., et al. (2017). A 673 μW 1.8-to-2.5 GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications. In IEEE international solid-state circuits conference (pp. 420–421).