GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC
Author:
Publisher
Springer Science and Business Media LLC
Subject
Computer Networks and Communications,Software
Link
http://link.springer.com/article/10.1007/s10586-017-0979-0/fulltext.html
Reference28 articles.
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3. Yaghini, P. M., Eghbal, A., Bagherzadeh, N.: A GALS router for asynchronous network-on-chip. In: Proceedings of International Workshop on Manycore Embedded Systems (MES ’14). ACM, New York, NY, USA. (2014). doi: 10.1145/2613908.2613918
4. Modular asynchronous network-on-chip: Application to GALS Systems Rapid Prototyping. In: Proceedings of IFIP TC 10, WG 10.5, 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), Perth, Australia, Springer US, 17–19 Oct 2005. doi: 10.1007/978-0-387-73661-7_13
5. Plana, L.A., Clark, D., Davidson, S., Furber, S., Garside, J., Painkras, E., Pepper, J., Temple, S.: SpiNNaker: design and implementation of a GALS Multicore System-on-Chip. J. Emerg. Technol. Comput. Syst. 7, 18 (2011)
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