Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates-Reference-Cited by-同舟云学术

Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates

Published:2018-03-26 Issue:S6 Volume:22 Page:15231-15244
ISSN:1386-7857
Container-title:Cluster Computing
language:en
Short-container-title:Cluster Comput

Author:

Naveen Balaji G.,Chenthur Pandian S.

Publisher

Springer Science and Business Media LLC

Subject

Computer Networks and Communications,Software

Link

http://link.springer.com/content/pdf/10.1007/s10586-018-2552-x.pdf

Reference19 articles.

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2. Priyadharshini S., Agarwal, V.D.: Dynamic SCAN clock control for test time reduction maintaining peak power limit. IEEE Test Symposium, 978-1-61284-656-9/11/2011 IEEE (2011)

3. Priyadharshini, S., Agarwal, V.D.: Externally tested SCAN circuit with built-in activity monitor and adaptive test clock. In: National Science Foundation, Grant CNS-0708962-2011 (2011)

4. Rashid, F., Agrawal, V.: Power problems in VLSI circuit testing. In: VLSI Design and Test Symposium 2012, Lecture Notes in Computer Systems 7373, Springer, Berlin, pp. 393–405 (2012)

5. Wang, S., Gupta, S.K.: DS-LFSR: a new BIST TPG for low heat dissipation. In: Proceedings International Test Conference, pp. 848–857 (1997)

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