Power Problems in VLSI Circuit Testing

Author:

Rashid Farhana,Agrawal Vishwani D.

Publisher

Springer Berlin Heidelberg

Reference22 articles.

1. Agrawal, P., Agrawal, V.D.: On Improving the Efficiency of Monte Carlo Test Generation. In: Digest of 5th International Fault Tolerant Computing Symp., Paris, France, pp. 205–209 (June 1975)

2. Agrawal, P., Agrawal, V.D.: Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Networks. IEEE Trans. Computers C-24, 691–695 (1975)

3. Agrawal, P., Agrawal, V.D.: On Monte Carlo Testing of Logic Tree Networks. IEEE Trans. Computers C-25, 664–667 (1976)

4. Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Springer (2000)

5. Eichelberger, E.B., Lindbloom, E.: Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test. IBM Jour. Research and Development 27(3), 265–272 (1983)

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