Lower bound estimation of hardware resources for scheduling in high-level synthesis-Reference-Cited by-同舟云学术

Lower bound estimation of hardware resources for scheduling in high-level synthesis

Published:2002-11 Issue:6 Volume:17 Page:718-730
ISSN:1000-9000
Container-title:Journal of Computer Science and Technology
language:en
Short-container-title:J. Compt. Sci. & Technol.

Author:

Shen Zhaoxuan,Jong Ching Chuen

Publisher

Springer Science and Business Media LLC

Subject

Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/BF02960762.pdf

Reference36 articles.

1. Hu Y, Carlson B S. A unified algorithm for the estimation and scheduling of data flow graphs.Journal of Circuit Systems and Computers, June, 1996, 6(3): 287–318.

2. Tiruvuri G, Chung M. Estimation of lower bounds in scheduling algorithms for high-level synthesis.ACM Trans. Design Automation of Electronic Systems, Apr., 1998, 3(2): 162–180.

3. Narasimhan M, Ramannjam J. On lower bounds for scheduling problems in high-level synthesis. InProc. 2000 Design Automation Conference, Los Angeles, CA, USA, June, 2000, pp.546–551.

4. Jain R, Parker A C, Park N. Predicting system-level area and delay for pipelined and non-pipelined designsIEEE Trans. CAD-ICAS, 1992, 11(8): 955–965.

5. Timmer A H, Heijligers M J M, Jess J A G. Fast system-level area-delay curve prediction. InProc. 1st Asian Pacific Conference on Hardware Description Languages Standards and Applications, Brisbane, Australia, Dec., 1993, pp.198–207.

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