Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-662-49283-3_3
Reference9 articles.
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3. Ayala, J.L., Sridhar, A., Cuesta, D.: Thermal modeling and analysis of 3D multi-processor chips. Integr. VLSI J. 43(4), 327–341 (2010)
4. Su, B., Gu, J., Shen, L., Huang, W., Greathouse, J.L., Wang, Z.: PPEP: online performance, power, and energy prediction framework and DVFS space exploration. In: 47th IEEE/ACM International Symposium on Microarchitecture, pp.445–457. IEEE Computer Society, Washington, DC (2014)
5. Cuesta, D., Risco-Martin, J.L., Ayala, J.L.: 3D thermal-aware floorplanner using a MILP approximation. Microprocess. Microsyst. 36(5), 344–354 (2012)
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