Variation-aware fault modeling

Author:

Hopsch Fabian,Becker Bernd,Hellebrand Sybille,Polian Ilia,Straube Bernd,Vermeiren Wolfgang,Wunderlich Hans-Joachim

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference38 articles.

1. ITRS. International Technology Roadmap for Semiconductors. 2009 ed. http://www.itrs.net/Links/2009ITRS/Home2009.htm

2. Hapke F, Krenz-Baath R, Glowatz A, et al. Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. In: Proceedings of IEEE International Test Conference, Austin, Texas, USA, 2009. Paper 1.2

3. Ferguson F J, Shen J. Extraction and simulation of realistic CMOS faults using inductive fault analysis. In: Proceedings of IEEE International Test Conference, Washington DC, USA, 1988. 475–484

4. Shen J P, Maly W, Ferguson F J. Inductive fault analysis of NMOS and CMOS circuits. IEEE Des Test, 1985, 2: 13–26

5. Khare J, Maly W. From Contamination to Defects, Faults and Yield Loss. Dordrecht: Kluwer Academic Publishers, 1996

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-05

2. Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors;Science China Information Sciences;2013-02-19

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