Author:
Zhang Jingyu,Guo Minyi,Wu Chentao,Chen Yuanyi
Publisher
Springer Science and Business Media LLC
Reference39 articles.
1. Chou C, Jaleel A, Qureshi M K. BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. ACM SIGARCH Comput Arch News, 2016, 43: 198–210
2. Hudec B, Hsu C W, Wang I T, et al. 3D resistive ram cell design for high-density storage class memory—a review. Sci China Inf Sci, 2016, 59: 061403
3. Lun Z Y, Du G, Zhao K, et al. A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory. Sci China Inf Sci, 2016, 59: 122403
4. Lee Y, Kim J, Jang H, et al. A fully associative, tagless DRAM cache. In: Proceedings of ACM/IEEE International Symposium on Computer Architecture, Portland, 2015. 211–222
5. Hameed F, Bauer L, Henkel J. Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. In: Proceedings of Design, Automation and Test in Europe, Grenoble, 2013. 77–82
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