A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

Author:

Hou ZhongYuan,Yang Fan,Liu JunHua,Zhang Xing

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference10 articles.

1. Loke A L S, Barnes R K, Wee T T, et al. A versatile 90-nm CMOS charge pump PLL for SerDes transmitter clocking. IEEE J Solid-State Circ, 2006, 41: 1894–1907

2. Wang Y Y. The driving force for development of IC and system in future: reducing the power consumption and improving the ratio of performance to power consumption. Sci China Inf Sci, 2011, 54: 915–935

3. Yokoyama-Martin D A, Krishna K, Stonick J, et al. A multi-standard low power 1.5–3.125 Gb/s serial transceiver in 90 nm CMOS. In: IEEE Custom Integrated Circuits Conference, San Jose, 2006. 401–404

4. Nishi Y, Abe K, Ribo J, et al. An ASIC-ready 1.25–6.25 SerDes in 90 nm CMOS with multi-standard compatibility. In: IEEE Asian Solid-State Circuits Conference, Fukuoka, 2008. 37–40

5. Vamvakos S D, et al. A 2.488-11.2 Gb/s multi-protocols SerDes in 40 nm low-leakage CMOS for FPGA applications. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, 2012. 5–8

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