Author:
Chen YingMei,Wang Hui,Yan ShuangChao,Zhang Li
Publisher
Springer Science and Business Media LLC
Reference15 articles.
1. Savoj J, Razavi B. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. IEEE J Solid-State Circ, 2003, 38: 13–21
2. Chen Y M, Wang Z G, Zhang L. A low-jitter low-power monolithically integrated optical receiver for SDH STM-16. Sci China Inf Sci, 2011, 54: 1293–1299
3. Lee J, Razavi B. A 40 Gb/s clock and data recovery circuit in 0.18-um CMOS technology. IEEE J Solid-State Circ, 2003, 38: 2181–2190
4. Liu H Q, Goh W L, Siek L, et al. A low-noise multi-GHz CMOS multiloop ring oscillator with coarse and fine frequency tuning. IEEE Trans Very Large Scale Integr Syst, 2009, 17: 571–577
5. Chu H L, Hsieh C L, Liu S L. 20 Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13 μm CMOS. In: IEEE Asian Solid-State Circuits Conference, Fukuoka, 2008. 429–432
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献