A 12 Gbps DES Encryptor/Decryptor Core in an FPGA-Reference-Cited by-同舟云学术

A 12 Gbps DES Encryptor/Decryptor Core in an FPGA

Published:2000 Issue: Volume: Page:156-163
ISSN:0302-9743
Container-title:Cryptographic Hardware and Embedded Systems — CHES 2000
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Author:

Trimberger Steve,Pang Raymond,Singh Amit

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-44499-8_11

Reference7 articles.

1. ANSI, “Triple Data Encryption Algorithm Modes of Operation”, American National Standards Institute X9.52-1998, American Bankers Association, Washington DC, July 29, 1998

2. FIPS, “Data Encryption Standard”, Federal Information Processing Standards Publication 46-2, 1993 December 30.

3. Kwan, M., “Bitslice DES”, http://www.darkside.com.au/bitslice/ nonstd.c

4. 5. Patterson, C., “High Performance DES Encryption in Virtex FPGAs using Jbits”, FCCM 2000, IEEE Computer Society, 2000.

5. Patterson, C., private communication, 2000.

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