Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES-Reference-Cited by-同舟云学术

Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES

Published:2003 Issue: Volume: Page:181-193
ISSN:0302-9743
Container-title:Field Programmable Logic and Application
language:
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Author:

Rouvroy Gaël,Standaert François-Xavier,Quisquater Jean-Jacques,Legat Jean-Didier

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-45234-8_19

Reference17 articles.

1. Rabaey, J.M.: Digital Integrated Circuits. Prentice Hall, Englewood Cliffs (1996)

2. Xilinx: Virtex 2.5V field programmable gate arrays data sheet, available from http://www.xilinx.com

3. Xilinx, Pasham, V., Trimberger, S.: High-Speed DES and Triple DES Encryptor/ Decryptor (August 2001), available from http://www.xilinx.com/xapp/xapp270.pdf

4. Schneier, B.: Applied Cryptography, 2nd edn. John Wiley & Sons, Inc., Chichester (1996)

5. National Bureau of Standards. FIPS PUB 46, The Data Encryption Standard. U.S. Departement of Commerce (January 1977)

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