Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams-Reference-Cited by-同舟云学术

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Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams

Published:2001 Issue: Volume: Page:387-390
ISSN:0302-9743
Container-title:Computer Aided Verification
language:
Short-container-title:

Author:

Amla Nina,Emerson E. Allen,Kurshan Robert P.,Namjoshi Kedar

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-44585-4_38

Reference13 articles.

1. Lect Notes Comput Sci;N. Amla,2000

2. Lect Notes Comput Sci;N. Amla,2001

3. T. Amon, G. Borriello, T. Hu, and J. Liu. Symbolic Timing Verification of Timing Diagrams Using Presburger Formulas. In DAC, 1997.

4. A. Benveniste. Safety Critical Embedded Systems Design: the SACRES approach. Technical report, INRIA, May 1998. URL: http://www.tni.fr/sacres/index.html .

5. U. Brockmeyer and G. Wittich. Tamagotchis need not die-Verification of STATEMATE Designs. In TACAS. Springer-Verlag, March 1998.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An evaluation of timed scenario notations;Journal of Systems and Software;2010-02

2. Visual Specifications for Modular Reasoning about Asynchronous Systems;Formal Techniques for Networked and Distributed Sytems — FORTE 2002;2002

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