Tamagotchis need not die — Verification of statemate designs-Reference-Cited by-同舟云学术

Tamagotchis need not die — Verification of statemate designs

Published:1998 Issue: Volume: Page:217-231
ISSN:0302-9743
Container-title:Tools and Algorithms for the Construction and Analysis of Systems
language:
Short-container-title:

Author:

Brockmeyer Udo,Wittich Gunnar

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/BFb0054174

Reference19 articles.

1. S.B. Akers: Binary decision diagrams. In: Transactions on Computers, No. 6 in Vol. C-27, IEEE (1978) 509–516

2. K. S. Brace, Richard L. Rudell and Randal E. Bryant: Efficient implementation of a BDD package. In: Proceedings 27th Design Automation Conference, Orlando, Florida, ACM/IEEE (1990) 40–45

3. J.R. Burch, E.M. Clarke, K.L. McMillan and D.L. Dill: Sequential circuit verification using symbolic model checking. In: Design Automation Conference ACM/IEEE (1990)

4. J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill and Jim Hwang: Symbolic model checking: 1020 states and beyond. In: Proceedings of the Fifth Annual IEEE Symposium on Logic in Computer science (1990)

5. W. Damm, U. Brockmeyer, H.J. Holberg, G. Wittich and M. Eckrich: Einsatz formaler Methoden zur Erhöhung der Sicherheit eingebetteter Systeme im KFZ. VDI/VW Gemeinschaftstagung (1997)

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Integrated Model-Checking for the Design of Safe and Efficient Distributed Software Commissioning;Lecture Notes in Computer Science;2019

2. A NEW APPROACH TO VERIFY STATECHART SPECIFICATIONS FOR REACTIVE SYSTEMS;International Journal of Software Engineering and Knowledge Engineering;2008-09

3. Structure Preserving Data Abstractions for Statecharts;Formal Techniques for Networked and Distributed Systems - FORTE 2005;2005

4. Specification and Formal Verification of Temporal Properties of Production Automation Systems;Integration of Software Specification Techniques for Applications in Engineering;2004

5. Model Checking Synchronous Timing Diagrams;Formal Methods in Computer-Aided Design;2002