Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing

Author:

Amira Abbes,Bouridane Ahmed,Milligan Peter

Publisher

Springer Berlin Heidelberg

Reference9 articles.

1. W.B. Ligon III, S. McMillan and al., “A re-evaluation of the practicality of floating-point operation on FPGAs.” IEEE Symposium on FPGAs for Custom Computing Machines, pp. 206–215, April 15–17, 1998.

2. Lect Notes Comput Sci;J. Poldre,1999

3. D.A. Patterson, J.L. Hennessy, and D. Goldberg, “Computer Architecture, A Quantitative Approach.” Appendix A, second ed. Morgan Kaufmann, 1996.

4. P. Graham and B. Nelson “FPGA-Based Sonar Processing.” Proceedings of the sixth ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA 1998), February 22–25 2001, Monterey, CA, USA.

5. A. Amira, A. Bouridane, P. Milligan and P. Sage “A High Throughput FPGA Implementation of A Bit-Level Matrix Product.” Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation (SIPS), pp 356–364, October 2000, Lafeyette, LA, USA.

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