A matrix product accelerator for field programmable systems on chip-Reference-Cited by-同舟云学术

A matrix product accelerator for field programmable systems on chip

Published:2008-03 Issue:2 Volume:32 Page:53-67
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Zicari Paolo,Corsonello Pasquale,Perri Stefania,Cocorullo Giuseppe

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference18 articles.

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3. Melbourne K.N. To, W. Marwood, C.C. Lim, M.J. Liebelt, A.J. Beaumont-Smith, Simulated performance of selected signal processing algorithms on the MatRISC architecture, in: The fourth International Conference on Optimization: Techniques and Applications, Perth, Australia, December 1998.

4. J. Jang, S. Choi, V.K. Prasanna, Area and time efficient implementations of matrix multiplication on FPGAs, in: IEEE International Conference on Field-Programmable Technology, Hong Kong, December 2002.

5. O. Mencer, M. Morf, M. Flynn, PAM-Blox: High performance FPGA design for adaptive computing, in: IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, April 1998.

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